Design kit with layout views for 1.8V pads (or lower)

Does anybody happen to know about a design kit for Cadence that includes 1.8V I/O pads with layout views, or lower?

I need these views in order to perform a detailed analysis of the pad parasitic loading and its coupling to the power lines, by means of post-layout simulations. I am developing a new transceiver for a parallel intra-chip communication bus, and I have realized that I need to take into account these effects with great detail, because they could easily render the whole communication scheme unusable.

The only process that we have access to that include these views are 0.35um or larger, with 3.3V I/Os. My scheme works fine with such large I/O voltage, but we need to asses its operation with much lower voltage pads (1.8V or even lower). We have access to various smaller TSMC and UMC processes (180nm to 90nm) with their corresponding standard cells (Faraday and ARM), but the I/Os provided by these companies DO NOT INCLUDE LAYOUT VIEWS, and after contacting them they have made it clear that they DO NOT provide those views; never, ever.

I have also taken a look to the NCSU and FreePDK free kits, but they only provide pad cells for 0.35um processes, wich are also 3.3V!

Any suggestions on how can I surmount this problem are welcome!

Regards,

Jorge.

P.S. Note: designing the pads myself is not an option: they have to be silicon-proven already (and it would also take me ages to acquire the required expertise!).

ibm 130nm has characterized bondpads as part of the pdk

Thanks for your reply, oermens. Are you talking about the 8WL and 8HP processes available through MOSIS? In their website it says that the I/O voltages for these processes are 2.5/3.3V, which are the same as those in the previous generation 180nm processes 7WL and 7HP. I had access to the 7WL design kit but it didn't include layout views of the I/O pads. Could you please confirm the existence of these views in the 180nm version of the PDK?

The processes you mentioned are SiGE, not CMOS. The CMOS 130nm kit from IBM is 8RF. See IBM 0.13 Micron 8RF-DM Process

I think I misunderstood, I was looking at core voltages not I/O. For 1.8 V I/O try IBM 65 Nanometer 10SF Process IBM 65nm

MOSIS' page about the design kits available for the 65nm 10SF technology lists "ESD Toolbox2, ARM, and Aragio" (IBM Design Kits (CMOS)).
Do you know if any of these libraries include I/O cells with layout views that could be used for running post-layout simulations including them? I suspect not...

standard cells do not give layout views, as far as i know. but the pdk itself should come with characterized bondpads (no esd or drivers) which have layout pcells.