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XSA-3S1000 SDRAM Controller

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smsarmad

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I want to implement a SDRAM controller to save data in the SDRAM of XESS XSA-3S1000 board. The data is actually pixel values that is received on the I/O proto pins of the board that are directly connected to the FPGA. I found a typical design of the controller in the attached pdf file but I couldn't understand the function of some signals like DQMH, DQML etc. So can somebody explain these signals. Besides that can somebody let me know what is the size of the SDRAM on this board.
 

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  • an-030104-sdramcntl.pdf
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A little more elaboration.

The Manual of the XSA-3S1000 board says that the SDRAM is of 32 MB and somewhere else in the same manual it is written "The XSA-3S1000 Board incorporates a 16M x 16 SDRAM.....", by which I understand that it has 16M rows and 16 columns.

Moreover in diagrams of the manual they have shown that the Data Bus size is 16-bit and Address Bus size is 15-bit (2-bit Bank Address + 13-bit Address).

Now I don't get how a 15-bit bus can access 16M(=16777216) locations as 2^15 equals 32768.

So plz someone tell me how is this being done?
 

The manual says:

A 256 Mbit SDRAM provides volatile data storage accessible by the FPGA.
Click to expand...
Which means 32 Mega words x 16 bits = 256Megabits

The SDRAM used on this board is Samsung K4S561632E**broken link removed**

The address you are referring to are the physical address of the SDRAM (if you look at the datasheet they are the ones referred to as A0-A12) and the the 2 column addresses are BA0-1. How the SDRAM controller communicates with the FPGA is something you have to look into the documentation of the XESS but this is how the interface that. I would guess that the address is 32 bit with the first 25 bits being valid for this specific SDRAM.

Best regards,
/Farhad
 

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