wangje
Newbie level 1
Need help with DDR2 PHY design
I'm creating a desgin what shares the interface with another
DDR2 SDRAM. Which means the block has to act as it's
an DDR2 SDRAM, which needs to meet the same timing
requirements as a DDR2 SDRAM.
My challenge is on the PHY interface. I have designed the DDR2
PHY interface that talks to DDR2 SDRAM, but not the other way
around. Can anybody suggest any sample design or reading
material other than JEDEC spec.?
My first challenge is to meet the tDQSCK requirement.
Any suggestion is welcome!
Many Thanks,
I'm creating a desgin what shares the interface with another
DDR2 SDRAM. Which means the block has to act as it's
an DDR2 SDRAM, which needs to meet the same timing
requirements as a DDR2 SDRAM.
My challenge is on the PHY interface. I have designed the DDR2
PHY interface that talks to DDR2 SDRAM, but not the other way
around. Can anybody suggest any sample design or reading
material other than JEDEC spec.?
My first challenge is to meet the tDQSCK requirement.
Any suggestion is welcome!
Many Thanks,
Last edited: