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how to add I/O pad to my verilog code (backend with Astro)?

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sicheng163

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Hi,all
I got some problems about I/O pad insertion in Astro,

1. one way is to make a core gds file, then import gds file to make a reference library, finally write a top .v file contain I/O pad and core macro, but when import gds file I got a lot of warning like this:
cell [DFFRX4TS] is not defined, ref ignored
Click to expand...
all std cell seems not defined... so I can't work on

2. another way is to import std cells and I/O pad at the same time, but I don't know how to write the whole verilog file, that is I don't know how to combine .v file synthesized by DC and the I/O .v file?
anybody help me?

thanks!!
 

the best way is to include the IO pad in your RTL code, as macro module, like memories.
 

rca said:
the best way is to include the IO pad in your RTL code, as macro module, like memories.
Click to expand...
thanks, you mean I should contain I/O pad in RTL code before DC synthesis?
then is there any differences with my Timing Constraint file(sdc) ? maybe I should define set_input_delay or set_output_delay more accurate?
anyway, I think you have hinted me a lot, thanks again.
 

Hi,

If you add them at physical design step, then you'll modify the front end netlist, and it will be like an ECO. Then you will not be able to do formality between previous front end netlist (reference netlist) and post layout one.

Furthermore you'll need to write/modify new constraints for these signal pads.

What I see in our designs is IO pads for "signals" are inserted at front end (at RTL/Synthesis stage). Constraints are written/updated according to added signal pads. However, IO pads for power/ground nets are inserted at physical design step (astro/magma/icc etc...).

Therefore it seems that adding "signal pads" before physical design step is less painful. On the other hand, there can be other approaches of course.

Best regards,
Gokhan
---
 

GI said:
Hi,

If you add them at physical design step, then you'll modify the front end netlist, and it will be like an ECO. Then you will not be able to do formality between previous front end netlist (reference netlist) and post layout one.

Furthermore you'll need to write/modify new constraints for these signal pads.

What I see in our designs is IO pads for "signals" are inserted at front end (at RTL/Synthesis stage). Constraints are written/updated according to added signal pads. However, IO pads for power/ground nets are inserted at physical design step (astro/magma/icc etc...).

Therefore it seems that adding "signal pads" before physical design step is less painful. On the other hand, there can be other approaches of course.

Best regards,
Gokhan
---
Click to expand...

thanks a lot, I'll try to add I/O pads in RTL code.
 

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