Design Compiler Verilog output - in a single module

Hello,

I have a VHDL multiplier design that I am trying to synthesize with Design Compiler. The output is correct and verified through simulation, but it is being broken up into different modules, with some of the modules making calls to the other modules.

I would like to generate the verilog gate-level netlist with all of the code in a single module. Is there a way to achieve this?

I have found an online reference that states "When Design Compiler performs logic optimization on a design, it can restructure all or part of the design. You have control over the degree of restructuring. You can keep your design’s hierarchy intact, move modules up or down the design hierarchy, combine modules, or compress the entire design into one module" but it does not specify how to actually do it.

Thanks.

I haven't synthesized VHDL before, but I assume DC works the same way as Verilog.

You just need to ungroup all the modules with ungroup command(like ungroup -all -flatten on the top level module)

Just what I needed, thanks!

You have generated hierarchical netlist, you can flatten the netlist as mentioned.