Malek Lamari
Member level 4
Hi,
I want to know if it is possible to use Tanner EDA to develop IC devices and then export the mask or the final netlist to Silvaco environment in order to simulate the type out process (Lithography ...).
If this is possible, this will allow us to simulate the hole IC design process.
Thanks in advance.
I want to know if it is possible to use Tanner EDA to develop IC devices and then export the mask or the final netlist to Silvaco environment in order to simulate the type out process (Lithography ...).
If this is possible, this will allow us to simulate the hole IC design process.
Thanks in advance.