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regarding timing Design rule constraints

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wafer

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Hi,
I wanted to know what parameters decide max capacitance, max transition and max fanout constraints in sdc? what decides to what values we should set these values to?
 

I think most of the people set max transition based on their experience because max transition could affect a lot on the cell count, power, and timing and they know a good compromising point from the experience, but if you want to set it methodologically, one of the ways is setting max transition based on the timing arc in the library. i.e. it doesn't exceed the range used in the timing arc so that the timing calculation doesn't go extrapolation.
Max cap and fanout are difficult to formulate and I usually don't pay too much attention to them since when the transition time is reasonable, cap and fanout shouldn't be that bad.
 
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in general, this parameter are define in the std cell liberty file.
 

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