rohscomplaint
Newbie level 5
Slew rate is the output voltage rate in unit time slot.
However, as far as I know the output voltage change rate also depends on the load.
If the load is a capacitor, the voltage change will be slower.
How is the slew rate value in datasheet derived, I mean, the datasheet slew rate value is tested under which condition? No load?
In the FPGA output configuration, there are many slew rate standard, SLOW, FAST...
I tried to change the different slew rate in FPGA configuration under same driven strength, but I can't find any difference when observing with oscilloscope.
Thanks!
-Rohs
However, as far as I know the output voltage change rate also depends on the load.
If the load is a capacitor, the voltage change will be slower.
How is the slew rate value in datasheet derived, I mean, the datasheet slew rate value is tested under which condition? No load?
In the FPGA output configuration, there are many slew rate standard, SLOW, FAST...
I tried to change the different slew rate in FPGA configuration under same driven strength, but I can't find any difference when observing with oscilloscope.
Thanks!
-Rohs