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Confused with slew rate.

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rohscomplaint

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Slew rate is the output voltage rate in unit time slot.
However, as far as I know the output voltage change rate also depends on the load.
If the load is a capacitor, the voltage change will be slower.
How is the slew rate value in datasheet derived, I mean, the datasheet slew rate value is tested under which condition? No load?

In the FPGA output configuration, there are many slew rate standard, SLOW, FAST...
I tried to change the different slew rate in FPGA configuration under same driven strength, but I can't find any difference when observing with oscilloscope.

Thanks!

-Rohs
 

The load should be stated in the data sheet. Usually it is 50 ohm resistive load and a specified maximum capacitance. If you measured the slope in high impedance you would not see any difference.
 

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