multiple input XNOR gate using the virtex II Pro BUFT

Gooday,

I am trying to implement a multiple input XNOR gate using the virtex II Pro unisim primitive BUTF. My VHDL code is as follows:

library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;


entity BUFT_XNOR is
port (
E_0, E_1, E_2, E_3 : in std_logic ;
enable : out std_logic );
end BUFT_XNOR ;

architecture XNOR_BUFT of BUFT_XNOR is


begin

DFF_Enable_0 : BUFT port map ( enable, E_0, E_3 );
DFF_Enable_1 : BUFT port map ( enable, E_1, E_0 );
DFF_Enable_2 : BUFT port map ( enable, E_2, E_1 );
DFF_Enable_3 : BUFT port map ( enable, E_3, E_2 );

PULLUP_Enable : PULLUP port map (enable);
PULLDOWN_Enable : PULLDOWN port map (enable);
end XNOR_BUFT;

The code compiles fine, but when I simulate with Multisim, I get the output at shown in the attachment:



The Schematic:



Can anyone please tell me why I get the undefined output when one of the inputs is logic 1, and how to get the correct output.

Thank You.

F.

I prefer you to read the definition of BUFT, you may be done something wrong.
Be sure about it

I.A

Added after 2 minutes:

**broken link removed**

I'm not about to think this through, but just as a couple quick thoughts. You have a pullup and pulldown on enable... That sounds pretty wrong to me.

Also when setting e0 to high and e1-e3 low, you have enable0 driving high and enable3, enable4 driving low. (enable2 is tristated.)

you do realize that when t is high, then the buffer is tristated ie not driving a value. when it is 0, then it is driving a value.

nachum

Nachum is right, it's not driving value when it's one. You can aslo check for technology schematic to be sure.

Because, while I was doing a project and using tri-state buff with enable '1', it was inverted first...