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problem with SAR ADC design in Cadence ?

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piyush.kanodiya

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Hello,

i am working on SAR ADC design in cadence schematic composer..i am getting proper ouput from shift register but after shift reg. to SAR register ,not getting proper output...can any one help me?
for 5-bit DAC , shift register output is 10000 but therotically,we get out of 2.5v for vref=5v..but practically, i get 0.3125mv.. and one output for LSB from SAR Register...


thanks in advance,
Piyush
 

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