pawangupta
Junior Member level 1
Hi all,
I had done logical synthesis using SYnplify Premier & PAR with ISE..All timing constraints were meeting while after logic synthesis doing physical synthesis is giving timing error (-ve slack)....how it could happen...Can anybody explain it...
I had done logical synthesis using SYnplify Premier & PAR with ISE..All timing constraints were meeting while after logic synthesis doing physical synthesis is giving timing error (-ve slack)....how it could happen...Can anybody explain it...