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Mismatch variations in input differential pair -

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EmbdASIC

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I have a four stage amplifier, which is very sensitive to mismatch variations. That is surely visible by my monte carlo (process + mismatch) simulations.

Apparantly a 1% mismatch in input differential pair shifts the DC points to such a level that some transistors in the later stage leave saturation region, which is the reason for bad results in monte carlo sims.

A scaled size W/L does not control this mismatch problem, and i want to know how to optimize this circuit to make it more prone to mismatch variations.

Looking forward for some good suggestions.

Regards,
EA
 

For transistors that leave saturation across monte-carlo/corner runs imply that they have insufficient overdrive.
For mismatch, the general rule of thumb is to use a higher L. For input pairs, you need a large gm. For current mirrors, you need a high overdrive.
 

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    EmbdASIC

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Thanks for your input.
Lengths have been kept at 4xLmin. Moreover, what gm ratios do you think are sufficient between input pairs and mirror loads ?
 

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