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OPAMP differential pair mismatch?

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koka

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mismatched differential resistor pair

Hi~
Can anybody help me this? In my bandgap refernce design, the OPAMP was used to force 2 nodes in identical voltage level. However, in my silicon data, the negative input has ~100mV deviation measured from whole wafer (>100ea dice), but positive input node has very converged voltage appearance and it is close to simualtion result. The bandgap output looks functional in differet temp I tested. I don't think this is mismatch between the input pairs, can anybody have comment on this? thanks!
 

opamp mismatch, mv

Why do you measure inputs of OP AMP instead of bandgap output voltage. You can introduce additional capacitance or multimeter input resistance connected to ground in this node. As a result you can measure wrong value. The reason of that can be different: multimeter introduce additional current leakage into key node of bandgape reference. Parasitic capacitance can make that unstable and badgap will oscillate.
 

differential pair op amp

Thanks~ The negative and positive input paris are my reference nodes, the reason to do this is to see if voltage level is correct or not. The output voltage of bandgap looks correctly, but those reference nodes make me confused! If N input variation was introduced by parasitic R or C during the measurement, should I see the similar appearance from P input also? But this is not true.
 

What is current consumption of your bandgap? What is bipolar transistors ratio (including both current and area)?
 

The current consumpation is ~159uA, this value is close to my simulation. The bipolar transistor ratio is 16:2, emitter area is 10umX10um wide for each parasitic BJT, and current flow is ~16uA. By the way, if parasitic R and C is the reason, should I extend the test time to see the result again? (my test result was derived from automatic test equipment by wafer sorting).
 

The current consumpation is ~159uA, this value is close to my simulation. The bipolar transistor ratio is 16:2, emitter area is 10umX10um wide for each parasitic BJT, and current flow is ~16uA. By the way, if parasitic R and C is the reason, should I extend the test time to see the result again? (my test result was derived from automatic test equipment by wafer sorting).
 

You can simulate your schematic under your test condition. Add additional 10-20pF for wiring, 50 pF for tester input capacitance and 10M for tester input resistance. All these values not very precise but reasonable. You can look trough simulation results. May be it will help you to understand can testing enviroment affect on measurement result or not.
Good luck
 

Koka...I'm interested in your design and analysis problem! Could you attache the schematic here?

8O
 

I think the measurement setting unlikely bring so larger error.
add the testing parasitic, resimulating and told me your simulation resoluts
Pls add your schematic.
 

This should be a common result, a less than 10% variation result here.
It can blame to the gradient of doping, or a larger deviation of resistor you chose, or op-amp offset.
BTW, did you make these ratio resistors based upon a certain of unit size??

Regards,
 

Hi all~
Thanks for your help for my case. So far I have some concern to attach the schematic of this bandgap. By the way, the resistor ratio is 9.4/2um N+ Poly RPO resistor for each segment, and they are connected in series for higher resistance by inter-digit layout. Right now I am trying to make the "wait time" longer during my testing. Basically, I agreed that some parasitic C and R will be introduced during my meansuremnt. I wish I will see the positive news. I will also let you know that later.
 

Op-amp must keep the two nodes at the same potential .If this nodes are varying ,then low frequency Gain of the opamp is not very high .The other reason could be the two BJT's have not matched well leading to VBE mismatch.
 

Hi
I think you must be care
1. bandgap layout have good ground & Vbg volt = "you simulation result"

2. OPA input mismacth , you can find "device mismatch report from TXmc
Uxc .. and you can find mismatch depend on input diff pair W/L size
(you can not find it by hspice) another mismatch cause by body_effect
which type is your input diff pair ??

you can find many paper talk about diff_pair mismatch , if you can make
sure Vbg is ok ( use active Probe) then you can trace your ckt ..
as I know .25um process OPA mismatch usually small ..

deltaVt = A / ((WL)^0.5)

A = 8.11 3.3v nmos Uxc .25um process design data
= 7.09 3.3v pmos
= 5.16 2.5v nmos
=4.819 2.5v pmos
 

Hi, Andy2000!
You must specify units in expression.
W, L unit is "um"
deltaVt unit is "mV"
 

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