Need help on 2 simple Verilog questions

Can anyone help me to clarify the following verilog question?

Question 1:

always @(clk) begin
a = 0;
a <= 1;
$display(a);
end

I think the above verilog code will always display a= 0 all the time, am i correct?
Or will it display a= 0 at current clock cycle, and it will display a = 1 at next clock cycle?
Can anyone explain how this question works in detail?
I am still confused about blocking and nonblocking assignment in Verilog

Question2:

c = foo ? a : b;

For the above conditional statement, I know if foo = true(1), c=a, and foo = false(0) c=b. But what if foo = "x" value, what answer will i get?
Can anyone explain in detail?

Thank you

for second question answer is x
first question is more complicated.. first is you will never need such thing during your paractical rtl second is there is a very simple rule of blocking and non-blocking... use blocking assignments for synthesizable combinational verilog constructs and use non-blocking when making sequential circuit

-----------------------------
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
-----------------------------

Ans: The above simple verilog code always displays a = 0.

Reason:'a' is initialized 0 & 1 using BA & NBA Statements.according to the Verilog
Scheduling Schematics all the BA & $display stmts Executes First (i.e Active
Region).NBA is the 3rd region to execute.that is why always a value display
'0'.if you use $monitor(a),then a will be '1' bcoz $monitor() will execute in
the last region called 'postponed region'.

I Hope this explanation can clear your problem.

Thanks & Regards
Team CVC

-----------------------------
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
-----------------------------

First of all ..
above code will definitely show error while synthesis. you can not assign a single signal with BL and NBL statements.
And if you are only in terms of simulation

then a=1;

reason: first blocking assignment will assign a = 0; and at the end of non blocking assignment will store the previous value of 1 which is of course 1. so a will always be 1;

had it been a variable

initial begin
a<=0;
b=0;
end

always @(clk) begin
a = 0;
b=1;
a <= b; /////// b is not a register
$display(a);
end

Result a=1;

<= statement creates a flipflop or register so old and new values are defined with this. While = is a continuous assignment which does not translate into a register. so if right side of <= is not a register (as in case of b) left side variable will always get new value.

Now consider

initial begin
a<=0;
b<=0;
end

always @(clk) begin
a <= 0;
b<=1;
a <= b; /////// b is now a register, so a will get the old value
$display(a);
end

Result a=0;

hope thios helps

This is a tricky one! Verilog scheduling semantics basically imply a
four-level deep queue for the current simulation time:

1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue.

Only events in the active queue are completed this sim cycle, so the "a = 0"
happens, and then the display shows a = 0. If we were to look at the value of
a in the next sim cycle, it would show 1.