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    pid controller vhdl code

    i have to design a pid controller for controlling the duty cycle. the problem is wrote a vhdl code but they simulation results show undefind output of pid evry alternate clock cycle. i am not able to underdstand the problem.
    pls help.

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    pid controller vhdl code

    check for multiple drivers, or check the inputs to the assignment of the affected signal.


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    •   Alt12th August 2010, 21:32

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    Re: pid controller vhdl code

    i have already checked the code . i don't think dat there is prblm of multiple drivers. here is d code.

    pls lemme know the error in dis vhdl code .

    entity pid is
    port(
    u_out:out std_logic_vector( 15 downto 0);
    e_in:in std_logic_vector(15 downto 0);
    clk:in std_logic;
    reset:in std_logic);
    end pid;

    architecture Behavioral of pid is
    signal u1: std_logic_vector(15 downto 0);
    signal u_prev : std_logic_vector( 15 downto 0);
    signal e_prev1: std_logic_vector( 15 downto 0);
    signal e_prev2: std_logic_vector( 15 downto 0);
    constant k1: std_logic_vector( 6 downto 0 ):="1101011";
    constant k2:std_logic_vector( 6 downto 0):="1101000";
    constant k3: std_logic_vector( 6 downto 0) :="0000010";
    begin
    process( clk)
    begin
    if( clk'event and clk='1') then
    if reset ='1' then
    u_prev <="0000000000000000";
    e_prev1<="0000000000000000";
    e_prev2<="0000000000000000";
    else
    e_prev2<=e_prev1;
    e_prev1<=e_in;
    u_prev<=u1;
    u1<= u_prev + (k1*e_in)+(k2*e_prev2)+(k3*e_prev2);

    end if;

    end if;
    u_out<=u1;
    end process;
    end Behavioral;


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    pid controller vhdl code

    there are several things that can be done better. Here are my suggestions:
    1.) u1 needs some action on the reset. this is your issue.
    2.) really, it doens't need a reset at all. it could be moved out of the if-reset block.
    3.) e_prev2 appears for k2 and k3. this is probably a mistake.

    this does have a long longest path, so if a high clock rate is needed, you might need to do something to improve performance.

    Added after 45 seconds:

    also, none of the multiplies will be correct. the output of a*b is a vector of length len(a)+len(b).



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    Re: pid controller vhdl code

    In the above code the following statements are blocking statements:

    --first three statements happens in the first clock cycle.
    e_prev2<=e_prev1;
    e_prev1<=e_in;
    u_prev<=u1;
    --this statment happens in the 2nd clock cycle.So output comes every 2 clock cycle.
    u1<= u_prev + (k1*e_in)+(k2*e_prev2)+(k3*e_prev2);


    Use variables inside the process.Then it will work.

    --vipin
    http://vhdlguru.blogspot.com/



    •   Alt13th August 2010, 05:31

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    Re: pid controller vhdl code

    Quote Originally Posted by vipinlal

    Use variables inside the process.Then it will work.

    --vipin
    http://vhdlguru.blogspot.com/
    No It wont.

    U1 is never given a value.



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    pid controller vhdl code

    @Tricky : Why it will not work?
    The statement is similar to this right.
    u1<= u1 + (k1*e_in)+(k2*e_prev2)+(k3*e_prev2);

    What do you mean by it is never given a value.Can you explain more?
    If we admit that human life can be ruled by reason, then all possibility of life is destroyed.



    •   Alt13th August 2010, 08:29

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    Re: pid controller vhdl code

    thanks a lot for d suggestion .
    i have replaced e_prev2 e_prev1 . yes it was an error but then also it was still giving same result .
    then i tried using variable inside process then the output of pid was undefined for all the clock cycles.
    pls help



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    pid controller vhdl code

    post the new code again.
    If we admit that human life can be ruled by reason, then all possibility of life is destroyed.



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    Re: pid controller vhdl code

    here is the new code for pid
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.std_logic_unsigned.all;

    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    use IEEE.NUMERIC_STD.ALL;

    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity pid is
    port(
    u_out:out std_logic_vector( 15 downto 0);
    e_in:in std_logic_vector(15 downto 0);
    clk:in std_logic;
    reset:in std_logic);
    end pid;

    architecture Behavioral of pid is
    signal u1: std_logic_vector(15 downto 0);
    signal u_prev : std_logic_vector( 15 downto 0);
    signal e_prev1: std_logic_vector( 15 downto 0);
    signal e_prev2: std_logic_vector( 15 downto 0);
    constant k1: std_logic_vector( 6 downto 0 ):="1101011";
    constant k2:std_logic_vector( 6 downto 0):="1101000";
    constant k3: std_logic_vector( 6 downto 0) :="0000010";
    begin
    process( clk)
    --variable u1: std_logic_vector(15 downto 0);
    --variable u_prev : std_logic_vector( 15 downto 0);
    --variable e_prev1: std_logic_vector( 15 downto 0);
    --variable e_prev2: std_logic_vector( 15 downto 0);
    --constant k1: std_logic_vector( 6 downto 0 ):="1101011";
    --constant k2:std_logic_vector( 6 downto 0):="1101000";
    --constant k3: std_logic_vector( 6 downto 0) :="0000010";
    begin
    if( clk'event and clk='1') then
    if reset ='1' then
    u_prev <="0000000000000000";
    e_prev1<="0000000000000000";
    e_prev2<="0000000000000000";
    else
    e_prev2<=e_prev1;
    e_prev1<=e_in;
    u_prev<=u1;
    u1<= u_prev + (k1*e_in)+(k2*e_prev1)+(k3*e_prev2);

    end if;

    end if;
    u_out<=u1;
    end process;
    end Behavioral;


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    Re: pid controller vhdl code

    Can you try out this code and tell me what is the output?

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.std_logic_unsigned.all;
    
    entity pid is
    port(
    u_out:out std_logic_vector( 15 downto 0);
    e_in:in std_logic_vector(15 downto 0);
    clk:in std_logic;
    reset:in std_logic);
    end pid;
    
    architecture Behavioral of pid is
    
    begin
    process( clk)
    variable u1: std_logic_vector(15 downto 0);
    variable u_prev : std_logic_vector( 15 downto 0);
    variable e_prev1: std_logic_vector( 15 downto 0);
    variable e_prev2: std_logic_vector( 15 downto 0);
    constant k1: std_logic_vector( 6 downto 0 ):="1101011";
    constant k2:std_logic_vector( 6 downto 0):="1101000";
    constant k3: std_logic_vector( 6 downto 0) :="0000010";
    begin
    if( clk'event and clk='1') then
    if reset ='1' then
    u_prev :="0000000000000000";
    e_prev1:="0000000000000000";
    e_prev2:="0000000000000000";
    else
    e_prev2:=e_prev1;
    e_prev1:=e_in;
    u1:= u1 + (k1*e_in)+(k2*e_prev1)+(k3*e_prev2);
    
    end if;
    
    end if;
    u_out<=u1;
    end process;
    end Behavioral;
    --vipin
    http://vhdlguru.blogspot.com/


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  12. #12
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    Re: pid controller vhdl code

    i tried this code but simulation results show u_out as undefined for all the clock cycles. thanks a lot for help



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    pid controller vhdl code

    "1.) u1 needs some action on the reset. this is your issue."

    "No It wont.

    U1 is never given a value."

    u1 starts at xxxx. thus, on the first cycle, you will have: xxxx + 0000 + 0000 + 0000 = xxxx. the next cycle, xxxx + ...

    I suggest that variables never be used to infer registers. its not that they can't, it's that it is more difficult to read/modify/write the code correctly.



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    Re: pid controller vhdl code

    So does this solve the problem while initializing u1?
    variable u1: std_logic_vector(15 downto 0):=(others => '0');



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    Re: pid controller vhdl code

    sorry i am not getting what should be done . could you please explain a bit more about the suggestion



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    Re: pid controller vhdl code

    i has simulated this code but i am not getting how to check the output



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