MULTI MODE MULTI CORNER ANALYSIS.

HI

Do we need seperate sdc's for doing multimode multi corner sdc or we can merge sdc and run the P & R.
Suppose we have funcitonal and Scan mode.
And these modes are both operating at different frequencies.
SO during optimization how tool decides which mode to take first if we merge both constraints in a single sdc.
Is it now better to make 2 different sdc's ?

Thanks

I prefer to separate the SDC file, to increase the readability.

one more remark, if you force the design to reach the maximum frequency in functional mode, for example, in scan mode, if the design must be able to reach the same frequency ?

the only difference could be between shift or capture, is it what you mean?

HI rca,

Thanks for the reply.

The design is operating at a different frequency for scan mode e.g 10Mhz
and it is operating at some (lets say)100Mhz for functional mode.

So in this case how tool choses between these paths and which path to optimize first ( taken if we have merged both constraints).

Also is readability the only parameter for making different sdc's ?

Also if you can elaborate more on ur line

"the only difference could be between shift or capture, is it what you mean?"

Thanks

during the shift, the logic flop are connected together, so the logic path is null, and timing contraints is worst for hold time but good for the setup time.
In capture, the circuit is place like the functional mode.
Then if your circuit should be able to reach the same frequency in both mode. I expect.

IF i understand that , a shift cycle will wrk at a different freq and capture cycle will work at a different freq , but why is that done ?

I means the worst path, is not during the shift phase but during the capture phase, so the design reachs the constraints during the capture phase it will reach during the shift phase.

What we generally do, only one SDC constraints that cover also the scan mode. So you have only one clock domain and one SDC file.

friend_333 said:

IF i understand that , a shift cycle will wrk at a different freq and capture cycle will work at a different freq , but why is that done ?

Click to expand...

The reason why shifting and capturing cycles use different frequency(Technically there is no such thing as clock frequency in capture mode because it's just a single pulse) is because you have to toggle the scan enable signal when you move from shift mode to cap mode, and from cap mode to shift mode. After loading the scan chain(scan_en=1), you have to bring scan_en down to 0 to allow the capturing path enabled and need to give a new scan_en value enough time to propagate to SE pins of all the flops. Until scan_en settles, you shouldn't toggle the clock therefore clock is usually held high or low for a long time between shifting operation and capture operation. That's what you're referring to as different frequency, I guess.
The same for capture mode to shift out mode.

As for the timing optimization, you can just run it in operation mode. The paths enabled in scan capture mode are mostly the same as those in operation mode , unless scan clock scheme is structured strangely, and as long as it's meeting functional clock speed, it will meet setup time in scan capturing mode(usually scan capturing paths are allowed to have huge cycle window because you cannot toggle the clock until scan_en propagates to SE pins of all the flops. Cap paths have that much amount of time to reach D input of the target flops.)
Only extra you have to do is hold analysis on shifting paths.

I think lostinxlation's reply is very clear.

Thanks for ur replies ....

We have scan clocks defined in sdc at the o/p of the Mux and while doing CTS do we need to specify any special constraints for these scan clocks ?

Thanks

It depends on how functional clocks and scan clocks are structured, like separate scan clocks are assigned to each functional clocks, or some functional clock domains share the same scan clocks etc..

So what things we should take into consideration while doing CTS for scan ?