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How many transistors will be inferred for D flip flop in this synthesis ?

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vivek_p

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Synthesis

reg a;
wire b;

always@(posedge clk)
begin
if(rst)
a< =1'b0;
else
a <=b;
end


Here "a" is a D-Flip Flop. If I synthesis the design using Synopsys Design Compiler how many transistors will be inferred for "a"..............
 

Synthesis

eh, do you miss the rst signal on sensitivity list ?

if you have the spice model of the flip-flop of your target technolog, you can count the transistor.
 

Re: Synthesis

rca said:
eh, do you miss the rst signal on sensitivity list ?
Click to expand...
Not if he wants a synchronous reset.
 

Re: Synthesis

Please refer to the attachment for the equivalent hardware for the verilog provided above.

The exact gate count depends upon the mapping library used.

Suppose of the corresponding synopsis library has flip flop with synchronous reset, the synthesis just reports one flop.
Otherwise, the it reports a flop, and gate count required to map the MUX as part of combinational part.
 

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