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I don't know Allegro, but sometimes I just accept that I am going to get a DRC error with unusual structures. Vias in the power pad of SSOP/QFN packages for example. If I spent some time I might be able to construct things in a way that don't give an error, but that can take too much time.
regarding the vias on mounting hole i think you can place vias on the footprint itsself as pins (refer fig.)
while doing schematic include the vias in the symbol.
you may use shapes in Top layer for the breaks shown in figure.
If it still give errors means you can waive those errors (from display-->waive DRC--> waive) and this will eroors will be trated as 'known errors'
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thank you all reply. i got idea.