0 to 9999 bcd counter seven seg display code for beginners

its my first basic code which is completely working fine...

Its specially for all those beginners who dont know how to divide (decrease) the clock speed...

u can also check out my video => https://www.youtube.com/watch?v=RrPzS5FLz3k

codes are as follows:



Counter code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component clk_div
Port (
clk : in std_logic;
rst : in std_logic;
op : out std_logic
);
end component;

component segd
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal d: std_logic_vector(3 downto 0);
begin

c1: clk_div port map(clk,rst,flag);

process(rst,flag)
variable m0: std_logic_vector(3 downto 0):="0000";
variable m1: std_logic_vector(3 downto 0):="0000";
variable m2: std_logic_vector(3 downto 0):="0000";
variable m3: std_logic_vector(3 downto 0):="0000";

begin

if rst='0' then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= "1001" then
m0:= m0 + 1;
elsif m0="1001" and m1 /= "1001" then
m0:="0000";
m1:= m1 + 1;
elsif m1="1001" and m2 /= "1001" and m0="1001" then
m1:="0000";
m0:="0000";
m2:= m2 + 1;
elsif m2="1001" and m3/= "1001" and m0="1001" and m1="1001" then
m1:="0000";
m0:="0000";
m2 :="0000";
m3 := m3 + 1;
elsif m3="1001" then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
end if;
end if;

end process;

z0: segd port map(a,op0);
z1: segd port map(b,op1);
z2: segd port map(c,op2);
z3: segd port map(d,op3);

end count;






seven seg lookup table code:

library ieee;
use ieee.std_logic_1164.all;

entity segd is

port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end segd;

architecture sseg of segd is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;




most imortant CLOCK CODE:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity clk_div is
Port (
Clk : in std_logic;
rst: in std_logic;
op : out std_logic
);
end clk_div;

architecture RTL of clk_div is
constant max_count : natural := 6000000;

begin

compteur : process(Clk,rst)
variable count : natural range 0 to max_count;
begin
if rst = '0' then
count := 0;
op <= '1';
elsif rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTL;



If you get any quries about my code... then do comment..

Suggetions are also accepted...[/b]

Firstly, I would like to congratulate you on getting your code to work.

Unfortunantly, its generally not reccomended to write code like this. For college projects, its not bad though.

The biggest issue is the clock divider. For FPGA's, you have some dedicated clock resources. The fancier you get with code like above, the less likely you are to have the FPGA actually use the resources, or use them ideally. This can become an issue when you run the FPGA at higher clock rates, say 200MHz+.

Coding style itself is a preference. For example, I might have moved the assignments for "op" and "count" into seperate if-then-elses.

notice that op only has 2 conditions that matter "if less than max/2" and "if greater", while cnt has only 1 "if equal to max". In your case, this adds more logic for op -- op = 1 if less than max/2 or if equal to max.

In general, the more signals that are assigned in an if-then-else, the more likely you are to accidently add more logic then needed. for college classes, the goal is generally just getting something to work, so its not as big of an issue.

also, positional connections for instantiating components is generally avoided. It is a good way to waste time, make the code harder to read, write, and maintain. It can also lead to hard to find and confusing bugs. The rationale for making the code "more compact" isn't very good if you use a decent text editor.

You did use variables correctly, though I personally don't like using variables in clocked processes. The main issue is that it implies a different type of behavior. Its easy to accidently push though a register stage.

finally, a,b,c,d are not reset. this infers extra logic, or a latch. if reset is low and a clock occurs, these registers cannot change and are not reset.

Re: 0 to 9999 bcd counter seven seg display code for beginne

permute said:

Firstly, I would like to congratulate you on getting your code to work.

Unfortunantly, its generally not reccomended to write code like this. For college projects, its not bad though.

The biggest issue is the clock divider. For FPGA's, you have some dedicated clock resources. The fancier you get with code like above, the less likely you are to have the FPGA actually use the resources, or use them ideally. This can become an issue when you run the FPGA at higher clock rates, say 200MHz+.

Coding style itself is a preference. For example, I might have moved the assignments for "op" and "count" into seperate if-then-elses.

notice that op only has 2 conditions that matter "if less than max/2" and "if greater", while cnt has only 1 "if equal to max". In your case, this adds more logic for op -- op = 1 if less than max/2 or if equal to max.

In general, the more signals that are assigned in an if-then-else, the more likely you are to accidently add more logic then needed. for college classes, the goal is generally just getting something to work, so its not as big of an issue.

also, positional connections for instantiating components is generally avoided. It is a good way to waste time, make the code harder to read, write, and maintain. It can also lead to hard to find and confusing bugs. The rationale for making the code "more compact" isn't very good if you use a decent text editor.

You did use variables correctly, though I personally don't like using variables in clocked processes. The main issue is that it implies a different type of behavior. Its easy to accidently push though a register stage.

finally, a,b,c,d are not reset. this infers extra logic, or a latch. if reset is low and a clock occurs, these registers cannot change and are not reset.

Click to expand...

Actually this is not my college project, i am just new to VHDL so tried to get the code working.

I was just using trial and error method to get it done.
I read VHDL primer but didnt understood much, as in that book it is not specified about HOW actual VHDL programming should be done.
I didnt understood the concepts about when to use signal or variable and when to use which datatype. I didnt know much name of books but now i bought Douglas Perry, lets see.

But thanks for your suggestion, i will keep those points in mind...

Any Teacher or Expert is always better than book..

Some thoughts:

1. Good job for including numeric std. But bad job for not actually using it. Get rid of the std_logic_unsigned/signed/arith packages and never use them again, even if you see examples using them. They were never a standard and things have moved on since Synopsis made them. Just many people read old examples and stick with them. VHDL is strongly typed - so use the types appropriatly (dont just stick with std_logic_vector).

2. For FPGAs - never do clock dividers with logic. Always use PLLs - thats what they are on the FPGA for. The main problem is skew and large fanouts you get with clocks, so stuff just wont work.

3. learn about the differences between variable and signal. As a beginner, I would stay clear of variables until you understand how they work.

4. Enjoy the book

Re: 0 to 9999 bcd counter seven seg display code for beginne

TrickyDicky said:

Some thoughts:

1. Good job for including numeric std. But bad job for not actually using it. Get rid of the std_logic_unsigned/signed/arith packages and never use them again, even if you see examples using them. They were never a standard and things have moved on since Synopsis made them. Just many people read old examples and stick with them. VHDL is strongly typed - so use the types appropriatly (dont just stick with std_logic_vector).

2. For FPGAs - never do clock dividers with logic. Always use PLLs - thats what they are on the FPGA for. The main problem is skew and large fanouts you get with clocks, so stuff just wont work.

3. learn about the differences between variable and signal. As a beginner, I would stay clear of variables until you understand how they work.

4. Enjoy the book

Click to expand...

Thanks for suggetions buddy..

I just want to ask a question, I didnt understood the PLL concept. I googled it but didnt got proper info. I am using Altera DE1 board. I didnt understood how to use those PLL which you say are available on FPGA. I use Quartus II 9.2v.

I would be great help if you explain the process.

The Cyclone 2 on the board you are using has 4 PLLs (phase lock loops). You can create them using the mega-wizard.

You only need to use PLLs if your clocks are unrelated. If you wanted to divide a signal rate by 2, you can generate and enable signal that changes on every clock.

Re: 0 to 9999 bcd counter seven seg display code for beginne

@TrickyDicky:

I tried using the Mega Wizard to create PLL, but it said that the o/p cant be of 1Hz or 0.5Hz. Its limiting the o/p for 24MHz i/p frequency.

This is true. to get very low frequencies in an FPGA, its generally advised to use "clock enables" in the logic. eg, inside a clocked process:
if en = '1' then
logic
end if;

and make it so the enable event happens 1 cycle out of every N cycles.


This is where my "college project" comment comes from. For college projects, the rates are exceptionally low, and very simple. the user is never affected by the clock skew or waste of resources. but if you take a 400MHz input an divide it into a 200M and 100M clock, you'll start to see lots of issues.

Re: 0 to 9999 bcd counter seven seg display code for beginne

I think, I should study this in detail first. Actually I have VHDL in my next year, but due to my damn intrest in these things I am doing it now.

I am now making a Real Time Clock, and I think a simple counter is better for my current project.

I am facing one problem in my project. I am able to get the clock o/p perfectly i.e. 1 sec tick, and then increment in mins and hours, only I am not able to do is manually setting the time. i tried to implement the interrupt in clock, but it gives error about the variables m0 m1 m2 m3 cant be configured or incremented from outside. I didint get the error actually. Lets see.

Re: 0 to 9999 bcd counter seven seg display code for beginne

A modified code (using integer datatype) is posted on my blog:

https://jimmy-embedded-c-n-vhdl.blogspot.com/