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28th July 2010, 22:19 #1
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floating point divider vhdl code or full architecture
HI my friends
I need a floating point divider to use as a part of a bigger divider,anyway i seriously need a floating point divider vhdl code(especially designed in ieee fp number format) or a detailed and simple block diagram that i can implement it in vhdl easily(or at least not in a long time).i found a vhdl code and a library in edaboard,but they werent very usefull.
please,someone can help me and send a vhdl code(especially for ieee fp numbers format) or block diagram or a good document.
thanks.

29th July 2010, 08:26 #2
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floating point divider vhdl code or full architecture
Xilinx and Altera both provide floating point IP cores.
Other than that, try looking on opencores.org

29th July 2010, 08:46 #3
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Re: floating point divider vhdl code or full architecture
I think there is a floating point package available.I guess it supports division for ieee format .
The name of the package is float_pkg_c.vhd
Download it from here:
http://www.vhdl.org/fphdl/
Also you can documentation about the package from the same site.
vipin
http://vhdlguru.blogspot.com/

29th July 2010, 09:51 #4
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floating point divider vhdl code or full architecture
You wont get any good synthesis results from the floating point package.

29th July 2010, 09:51

29th July 2010, 17:57 #5
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floating point divider vhdl code or full architecture
thanks.
I need a code or architecture that doesn't be complicated.packages are not described full in their document and i couldn't understand how they work exactly.
anyone has not a code that be written by him self or herself as a project???or an architecture that i can write a structural code for it.

29th July 2010, 22:34 #6
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floating point divider vhdl code or full architecture
But floating point is complicated.
The altera documentation is pretty good  its in the help.

30th July 2010, 11:59 #7
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Re: floating point divider vhdl code or full architecture
But floating point is complicated.
The IEEE float libraries are good for the basic float handling, but, as said, not actually synthesizable, because they miss any pipeline action that would be required for reasonable speed.
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30th July 2010, 15:03 #8
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floating point divider vhdl code or full architecture
thank you FvM
and other suggestions??!!!

30th July 2010, 15:03

3rd August 2010, 10:53 #9
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Re: floating point divider vhdl code or full architecture
i couldn't use fpu100.
i have all of the fpu100 files in a folder an my top level is fpu.vhd,but when i run it in quartus II,indicate an error "can't find fpupack or comppack in working directory".
do you know what is the problem.
also i changed the fpu to seperate parts,adder,divider,...,then used them,but again it didn't work.
i have attached my divider,would you check it and tell me what did i do wrong???

3rd August 2010, 10:53

3rd August 2010, 11:29 #10
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floating point divider vhdl code or full architecture
Yes  Quartus is looking for fpupack.vhd and comppack.vhd. They are not there. althought they dont appear to be required.
I would put these back in the project.

3rd August 2010, 14:11 #11
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Re: floating point divider vhdl code or full architecture
do you know what is the problem
Basically you have to know where the design compilers searches for files, how you set up libraries and packages.
The problem hasn't to do with the FPU project, I think.
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4th August 2010, 09:44 #12
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Re: floating point divider vhdl code or full architecture
You can use Convergence (Functional Iteration) Algorithms for division.
Then using this algo try to make matlab code and prove your algo once you get correct result then you can easily write synthesizable code for that.
HTH
Shitansh Vaghela

20th October 2010, 23:10 #13
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Re: floating point divider vhdl code or full architecture
Do you have the code with you?the matlab code and vhdl code?

2nd February 2012, 17:53 #14
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Re: floating point divider vhdl code or full architecture
I have this simple code i have writen for floating point addition, subtraction, multilication, division and square root. I will post it here the code for division:

 Company: Instituto Superior Técnico
 Prof: Paulo Alexandre Crisóstomo Lopes
 paulo.lopes@inescid.pt

 Create Date: 21:12:41 01/05/2012
 Design Name:
 Module Name: divider  Behavioral
 Project Name:
 Target Devices:
 Tool versions:
 Description: VHDL implementation of a 32 bit floating divider.
 Float format: sign  8 bits exponent + 127  23 bits normalized mantissa.
 Uses IEEE 7541985, with the following exceptions.
 NaN is not implemented. Operations that would result in NaN
 have a non definied result.
 An exponent of all zeros will always mean zero, and an
 exponent of all ones will always mean infinity.
 Rounding is round nearest ties away from zero.
 Non normalized numbers are not implemented.

 Dependencies:

 Revision:
 Revision 1.0
 Additional Comments:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
 use STD.textio.all;  basic I/O
 use IEEE.std_logic_textio.all;  I/O for logic types
entity divider is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));
end divider;
architecture Behavioral of divider is
begin
process(x,y)
variable x_mantissa : STD_LOGIC_VECTOR (22 downto 0);
variable x_exponent : STD_LOGIC_VECTOR (7 downto 0);
variable x_sign : STD_LOGIC;
variable y_mantissa : STD_LOGIC_VECTOR (22 downto 0);
variable y_exponent : STD_LOGIC_VECTOR (7 downto 0);
variable y_sign : STD_LOGIC;
variable z_mantissa : STD_LOGIC_VECTOR (22 downto 0);
variable z_exponent : STD_LOGIC_VECTOR (7 downto 0);
variable z_sign : STD_LOGIC;
variable a : STD_LOGIC_VECTOR (25 downto 0);
 holds the result of the division of the mantissas
 a = a0.a1a2a3... a<2 e a>1/2
 0 to 23 if a0=1 and 1 to 24 if a0=0. a25 to round.
variable partial_remainder : STD_LOGIC_VECTOR (24 downto 0);
 the partial remainder requires one extra bit for the shift left
 P = partial_remainder = xx.xxxx ... < 4
variable tmp_remainder : STD_LOGIC_VECTOR (24 downto 0);
variable exponent_aux : STD_LOGIC_VECTOR (8 downto 0);
 nine bits = 8+1 to detect underflow and overflow
begin
x_mantissa := x(22 downto 0);
x_exponent := x(30 downto 23);
x_sign := x(31);
y_mantissa := y(22 downto 0);
y_exponent := y(30 downto 23);
y_sign := y(31);
z_sign := x_sign xor y_sign;
if (y_exponent="11111111") then  x/inf = 0
z_exponent := "00000000";
z_mantissa := (others=>'0');
else
if (y_exponent=0 or x_exponent=255) then  result = infinity
 x/0 or inf/x = inf
z_exponent := "11111111";
z_mantissa := (others=>'0');
else
exponent_aux := ('0' & x_exponent)  ('0' & y_exponent) + 127;
partial_remainder := "01" & x_mantissa;  P = 1.F1
 Area with a comparator: 1,851 4 input LUT
 Area joining comparacion and subtraction: 1,324 4 input LUT
digit_loop: for i in 25 downto 0 loop
tmp_remainder := partial_remainder  ("01" & y_mantissa);
if ( tmp_remainder(24)='0' ) then
 result is non negative: partial_remainder >= ("01" & y_mantissa)
 note that tmp_remainder < 2 so bit 24 should be zero
a(i):='1';
partial_remainder := tmp_remainder;
else
a(i):='0';
end if;
partial_remainder := partial_remainder(23 downto 0) & '0';  sll
 P/2 < y && y < 2 => P < 4
end loop digit_loop;
a := a + 1;  round
if (a(25)='1') then  a=1.xxxx
z_mantissa := a(24 downto 2);
else  a=0.1xxxx
z_mantissa := a(23 downto 1);
exponent_aux := exponent_aux  1;
end if;
 z_exponent > 0254+1271 = 128 = 1 1000 0000 b
 y_exponent = 255 is infinity that was previously taken care
 z_exponent < 2550+127 = 382 = 1 0111 1110 b
if (exponent_aux(8)='1') then
if (exponent_aux(7)='1') then  underflow
z_exponent := "00000000";
z_mantissa := (others=>'0');
else  overflow
z_exponent := "11111111";
z_mantissa := (others=>'0');
end if;
else
z_exponent := exponent_aux(7 downto 0);
end if;
end if;
end if;
z(22 downto 0) <= z_mantissa;
z(30 downto 23) <= z_exponent;
z(31) <= z_sign;
end process;
end Behavioral;
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2nd February 2012, 19:25 #15
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Re: floating point divider vhdl code or full architecture
this code is pretty useless for a synthesised design (unless you dont mind a very very very slow design.
For a start  wheres the clock?

2nd February 2012, 19:53 #16
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Re: floating point divider vhdl code or full architecture
You could add a pipeline to the code if you wont.

6th March 2012, 08:37 #17
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Re: floating point divider vhdl code or full architecture
hi, i am also working on floating point alu & not getting proper output . please if u have floating point alu vhdl code ,please send it on my email id (prashant.khairnar17@gmail.com).

16th March 2012, 08:40 #18
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Re: floating point divider vhdl code or full architecture
Hi Paulo
Do you have the similar code for square root of 32 bit IEEE754 floating point. I have written a small function which can do unsigned square root.
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
 unsigned square root function function sqrt (vin : unsigned) return unsigned is variable v_in : unsigned(31 downto 0) := vin;  original input variable v_out : unsigned(15 downto 0) := (others => '0');  result variable i_left : unsigned(17 downto 0) := (others => '0');  input to adder variable i_right : unsigned(17 downto 0) := (others => '0');  input to subtractor variable remd : unsigned(17 downto 0) := (others => '0');  remainder variable i : integer:=0; begin for i in 0 to 15 loop i_right(0) := '1'; i_right(1) := remd(17); i_right(17 downto 2) := v_out; i_left(1 downto 0) := v_in(31 downto 30); i_left(17 downto 2) := remd(15 downto 0); v_in(31 downto 2) := v_in(29 downto 0);  shifting by 2 bit if (remd(17) = '1') then remd := i_left + i_right; else remd := i_left  i_right; end if; v_out(15 downto 1) := v_out(14 downto 0); v_out(0) := not remd(17); end loop; return v_out;  result end function sqrt;
Last edited by alexan_e; 16th March 2012 at 08:55. Reason: added SYNTAX tags

16th March 2012, 08:40

16th March 2012, 11:56 #19
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Re: floating point divider vhdl code or full architecture
Hi Paulo,
I saw your previous post regarding square root of IEEE754 floating point
http://www.edaboard.com/thread205274.html
I will pipeline the design for divider and square root logic.
Thanks
KS

15th February 2013, 06:17 #20
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