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FEEDBACK code IN VERLOG

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kunaldekate

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I am working on Arbiter where the algorithm is i-SLIP,
where i am using Verilog code and working on XILINX FPGA,
i am getting problem with feedback circuit where i am unable to conect my output to input with ctrl signal please help me
 

HDL attempts to generate hardware. You have defined a combinatorial loop. eg:
assign x = x +1;
makes no sense as a combinatorial circuit. It will work as a sequential circuit. eg:
always @ (posedge clk) x <= x +1;
 

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