Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

difference between an array of instance & generate for l

Status
Not open for further replies.
Y

yakovm

Newbie level 1
Joined
Jul 18, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,287
Hello
What is a difference between an array of instance and generate for
loop?
Thank you
 

in vhdl, an array of instance mean nothing.

a generate for loop, is useful when all input/output of this instance are in vector, and made the code simpliest.
 

Re: difference between an array of instance & generate f

generate statement is used repeating the port map for particular number of times.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top