Assura LVS is not stable

Hi everyone,

I've got a problem with Assura LVS. I don't understand why all of my digital circuits which used to pass LVS can't pass now. The process I use is IBM 65nm, they just updated the new PDK, so I thought it is due to the new PDK. However, when I used the old PDK that I had used before, it still didn't pass.
The mismatch is about the Drain and Source of the FET. For example, with a simple transmission gate consisting of 1 PMOS and 1 NMOS, in schematic, what we normally do is: the PMOS' S is connected to the NMOS' D as input, and the PMOS's D is connected to NMOS' S as output. In the layout, the 2 FETS are drawn correspondingly. Previously, this circuit had no problem, but recently, the mismatch came, it told me to swap the NMOS' S and D. I did and it passed. This happens to almost all the digital gates, it usually tells me to swap the FETs, even for a PMOS, what we normally do is connect the Source to VDD, but it tells to swap.
One more weird thing is that one circuit with the same PDK, the LVS passed, then 15' later it didn't, without any change.
Has anyone experienced this? I'm using Cadence 6.1.3 (on grid), Assura 3.2, IBM 65nm Lpe.
Thanks

Assura is a lot more whiney, and has a lot of options that occasionally
must be fiddled, than Diva. Used to be that permute rules would
take care of these S/D flips. I suspect there are some options that
do the same thing, only either set wrong for you or not set at all.

If it's passing and not-passing without rules deck or circuit changes,
that's peculiarly nondeterministic.

refer to release notes in your /Assura/doc folder to make sure you are using the correct version of Assura. Maybe the new PDK requires Assura41. Contact IBM (or your fab provider), our IBM 130nm kit also has Assura LVS problems in the most recent patch and they are working with Cadence to resolve the issue.

Thanks guys

The Assura version is compatible with the PDK.
I just did a test on an inverter in which both the FETs have 4 fingers. LVS never passes, in the layout it considers 4 fingers of each FET as 4 individual FETs while in the schmatic, there is only 1 FET.

Is there any settings to set this up?

jts said:

Is there any settings to set this up?

Click to expand...

Check if your LVS rules declare and use the parallelMOS procedure, s. p. 1 in the C@dence GPDK assuraLVS rules below.
Don't know if the mechanism is still the same.

Thanks guys,

I just found the problem, it is due to some initial settings when we first launch the Assura LVS run.