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Relation between lock range, cutoff frequency and phaseerror

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Gagan_SJSU

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hi all
I am working on a PLL. The maximum phase error that I can afford between my input and output is 2 degrees. The PLL lock range is 47Hz to 63Hz with a reference of 60Hz grid 3v peak to peak. VCO center frequency is 55Hz ...I am having too much phase lag...what is needed to reduce it....I am using a 2nd order LPF

-Resistance------------- VCO----output
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RESISTANCE
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CAPACITANCE
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gnd
 

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