S
somu.atluri
Guest
Hi,
I recently posted a question about 'how to test sram: generating the inputs'.
I would like to know, if I write a verilog code (which will have the test data inputs), is there a way to interface the verilog code with the schematic.
Thanks in advance for the help.
Ps: I have UltraSim & cadence virtuoso.
I recently posted a question about 'how to test sram: generating the inputs'.
I would like to know, if I write a verilog code (which will have the test data inputs), is there a way to interface the verilog code with the schematic.
Thanks in advance for the help.
Ps: I have UltraSim & cadence virtuoso.
