saharhamed
Newbie level 1
For 1 stage of the pipelined ADC
During the sampling time: the output of the pipelined ADC stage is zero,
During the amplification mode: the output equals the right expected value.
So when i put a second stage, its input (from the first stage) changes between the zero and the right value; therefore the output of the second stage becomes wrong because it doesn't see the right value all the time.
Do i have to put a sample and hold circuit after each stage?
During the sampling time: the output of the pipelined ADC stage is zero,
During the amplification mode: the output equals the right expected value.
So when i put a second stage, its input (from the first stage) changes between the zero and the right value; therefore the output of the second stage becomes wrong because it doesn't see the right value all the time.
Do i have to put a sample and hold circuit after each stage?
