vovan76
Junior Member level 3
Hi
I'm trying to simulate LDO stabilitybut there is som e unclear issue for me
what is LDO load - I mean :
I can put as load ideal current source and sweep on load currrent and check phase margin(PM)
and from other hand I can connect reditor insread the ideal current source and sweep on the registor value
But
if i take ideal source for I=100mA or resitor for same current I get about 20dB dc gain diference which influence on stability parrametrs
So what is the right LDO load for standart Analog circuit for stability simulation
Thanks
I'm trying to simulate LDO stabilitybut there is som e unclear issue for me
what is LDO load - I mean :
I can put as load ideal current source and sweep on load currrent and check phase margin(PM)
and from other hand I can connect reditor insread the ideal current source and sweep on the registor value
But
if i take ideal source for I=100mA or resitor for same current I get about 20dB dc gain diference which influence on stability parrametrs
So what is the right LDO load for standart Analog circuit for stability simulation
Thanks