options in specifying external_delay and set_input_delay

If there is only a 1GHz clock in this block, but there is an input signal that's changing every half nanosecond (change at both positive and negative edges of the 1GHz clock), how do I use external_delay (in RTL compiler) and use set_input_delay (in Encounter place&route) to let the tools know this? So that the tool checks setup time and hold time correctly...

The default of external_delay tells the tool that the input signal transitions relative to the positive edge of the clock... or negative edge only

set clk_1 [define_clock -period 1000 -name clk_1 Clk]

external_delay -input 150 -clock $clk_1 -name input_constraint1 -edge_rise [find /designs* -port ports_in/in* ]
external_delay -input 150 -clock $clk_1 -name input_constraint2 -edge_fall [find /designs* -port ports_in/in* ]

I do find out that if having two constraints on the same input port ( [find /designs* -port ports_in/in*] ) with different names, RTL Compiler will consider the input port changes 150ps after each edge of the clock (both positive and negative edges). That means, if the positive edge of clock is at 0, this input port changes at 150ps and 650ps.

Maybe this is not as useful. RTL Compiler fix setup time only, not for hold time anyway. I need ways to specify these kind of constraints in Encounter during place & route, so that it does setup and hold time analysis correctly for the input port. Anyone?

set_input_delay -clock [get_clocks {clk_1}] 0.150 [get_ports {in*}]
set_input_delay -clock [get_clocks {clk_1}] -clock_fall 0.150 [get_ports {in*}] -add_delay

The second "set_input_delay" does not overwrite the first one. Then Encounter will consider the input port changes 150ps after both positive and negative edges.