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turning diffrential mode LVPECL to single mode logic PECL

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yuval bnr

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helo all;
i am trying to take the SMA exit and to push it
into a comparator wich is Vcc 3.3v - LVPECL
and than to tow parallel logic components : XOR , and FLIPFLOP
both of them are PECL 5v Vcc.

i tried doing it like that but i am quite sure it wont work.
can someone pleas help me?

thnx
yuval
 

ECL gates can be operated as comparators if you don't mind low
gain and maybe some asymmetry from the not-balanced-
differential signal you describe.

If your input signal is continuous (like a clock) then a capacitor
level shift might do. Or if it has a guaranteed minimum
transition density like 8b/10b.

You might check whether one of the PECL families will tolerate
a lower common-mode input, allowing direct LVPECL to PECL
connection.

I bet somebody like ONSemi would have app notes regarding
this.
 

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