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Residual Phase Modulation in PLL output frequency

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afz23

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I have designed a 4GHz PLL frequency synthesizer using integer-N PLL chip.

Loop BW around 200KHz.

I have close-in phase-noise(at 100KHz offset ) of about -90dBc/Hz at PLL o/P(measured in spectrum analyzer).


I observe a residual PM 0f 0.1 radians p-p at PLL output(measured in modulation analyzer ),this value goes down to 0.02 rad if I select a LPF of 3KHz in Modulation analyzer,means some undesired frequency above 3KHz is modulating the carrier.Residual PM 0.1 radians is pretty high for a frequency synthesizer.

Experts please help, and suggest some measures to improve upon this.
 

Sounds like you need better close-in phase noise performance. Since your LBW is 200KHz I take it that the phase comparator operates at least at 5-10times that. I would make this as high as your channelisation and/or phase detector permits. The phase-noise of your reference also comes into play, so choose a good tcxo.
 

The pll chip from peregrine has certain limitations, it allows maxm comparison
frequency of 20MHz, I have taken 17MHz,Frf =3GHz (PE9704)

Phase noise performance for the PFD is governed by equation:
-210+10log(fc)+20log(N) dBc/Hz inside loop BW

-210 is PFD noise floor

fc =17MHZ,N=235

makes it -91dBc/Hz ,that's what we get practically, but residual PM is quite high
and I need solution to reduce it.
 

khanafzaal

I think what you are observing is absolutely normal.

If the PLL has a loop bandwidth of 200kHz, I do expect to have almost flat noise power from few kHz up to loop bandwith (-90dBc/Hz).

There is a math relationship between residual PM and phase noise, the first taking into account noise in overall bandwidth.

If you reduce the meas bandwidth by 100, if you noise density is flat, you will measure 1/100 of residual PM.

If you would like to understand better if there is a problem at certain frq offset, just measure the Phase noise from 1kHz to 10MHz and verify the results.

I hope it can help.

Mazz
 

Mazz
thanks for your comments

Please give maths relation between residual PM and Phase noise,also
please elaborate how residual PM is related to measurement BW,

As I decrease demodulator filter BW to 3KHz or 10KHz I see reduction
in residual BW.

How much phase noise will be equivalent to 0.02rad residual PM(required spec for me)?

Does that mean the above discussed intger-N PLL won't be able to give sufficiently
good Phase noise for my application?
 

Are you guys sure about your terminology? Don't you mean to say "the integrated phase noise is 0.1 radians"?

In the states, residual phase noise refers to "additive" phase noise of a certain component. Lets say you have a microwave amplifier and want to measure its additive phase noise to a system. You configure your measurement system to measure the amplifier's residual phase noise, while nulling out phase noise of the source in the test system.
 

PLL Phase Error RMS [°] = 107 x √ Loop_Bw [Hz] x 10^(Phase_Noise [dBc/Hz] / 20)
 

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    afz23

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Seems then that the only option left may be to narrow the LBW provided of course lock-in time and microphonics are not an issue. Phase noise-wise, you want to narrow your LBW until the in-band phase noise intersects the vco phase noise, which will be equal the pll in-band phase noise at an offset from carrier of, say, 1-10KHz for a very average vco.
 

biff44

you are right about terminology.
From the initial issue and explanation, I've been using it not to add another variable to the conversation. and it worked.

Vfone, thanks for the formula, you saved me time to find it.

khanafzaal
please be aware that the residual PM definition commonly is the one used by biff44. Please check your spec requirements (discussing with people who gave you).

4GHz PLL with in-band -90dBc/Hz is not so bad.

Mazz
 

thanks guys for giving your opinion on this topic, thanks vfone for that
formula.

The formula does fit for present case (200KHz LBW and -90dBc/Hz phase noise),it gives 1.5 deg rms phase error where as measured error is around 2 deg rms.

But for lower LBW say 20KHz the error goes down only slightly not as per formula.

Now in case I want to further improve phase noise at this PLL output ,as it will be used to generate higher frequencies by frequency multiplication, where 20logN will come into picture,plus residual phase will worsen.

What should I do?
Should I go for fractional N PLL where I can get better phase noise due to internal compensation or what should be the approach.
 

khanafzaal

first of all could you explain why you are using a 3GHz PLL if you need 4 GHz signal?

Is your loop BW=200kHz a required spec (for settling time, I suppose)?

Take a look at STW81102, it has up to 4 GHz output and 1.2deg RMS noise at 3.6GHz (better than your current system), but smaller loop bandwidth.

I hope it can help.

Mazz
 

you are right Mazz, the PLL chip is 3GHz and Peregrine is the manufacturer,

This is the only chip available to me for onboard application, which is is radhard
device ,Hi-rel ,proven in on onboard applications in many projects,for me heritage of chip is also important.

I am prescaling the VCO feedback signal below 3GHz for this application.
 

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