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Clock Duty Cycle in 8086

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pavan.emb

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Hi all,

I have one doubt regarding the clock duty cycle in 8086.

I am not that much familiar with 8086 processor..

but I read some where that 8086 has 33% duty cycle for clock frequency.

Can any one let me know why that is so?

where as in 8051 it is 50%...

let me some detailed explanation regarding these doubts.......

thanking you all.
 

Sorry for not having a proper answer, but this is all I could get from he net :

My guess would be that this is caused by a latch based design.

I guess that a structure as the one below might cause non
50% duty-cycle clocks to be more optimal although I don't have
any personal experience in designing such latch based designs:

Logic (with delay t)
|
V
Latch (Enabled by positive clk)
|
V
Logic (with delay 2*t)
|
V
Latch (Enabled by negative clk)

/Andreas
Click to expand...

This was Posted at : https://www.fpgarelated.com/usenet/fpga/show/79263-1.php
 

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