analog_fever
Junior Member level 3
I am designing a two stage filter to do decimation at the output of a Sigma Delta modulator. Here is the spec -
Sampling frequency - Fs - 1.4MHz
Decimation factor - D - 100
Output resolution - 13 bits.
The filter, and the modulator is reset every 100 clock cycles.
To accomplish this, I used a 5 stage CIC filter to decimate by 20 for the first stage. For the second stage I am hoping to use an LPF to decimate by 5.
1. Any suggestions on a multiplier free LPF implementation? IIR or FIR
2. Will a CIC work for the second stage also?
Sampling frequency - Fs - 1.4MHz
Decimation factor - D - 100
Output resolution - 13 bits.
The filter, and the modulator is reset every 100 clock cycles.
To accomplish this, I used a 5 stage CIC filter to decimate by 20 for the first stage. For the second stage I am hoping to use an LPF to decimate by 5.
1. Any suggestions on a multiplier free LPF implementation? IIR or FIR
2. Will a CIC work for the second stage also?
