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VHDL Syn in Design Compiler

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Aimerbhat

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I am using dc with standard LL 130nm library to synthesize a vhdl logic .

I removed the
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
and instead of std logic used bit and bit_vector in intialization
while analyzing in DC
analyze -library work -f vhdl {................}
i get an error
[Error] Expression error: no corresponding "+" operator defined for operand types

i am not able to figure out why this happening


thanks in advance
 

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