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synopsys- vcs to design_vision

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warlock_ajay

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Hi,

Few questions here. Please help.
I am working with some FDK, let's say UMC 180 CMOS

(pls correct me if I am wrong)


vcs:
1. I start with an rtl code and simulate it.
Q. Do I need to include the libraries for simulation from the FDK at this point?
How?
Q. In synopsys_sim.setup, what is the mapping for?

design_vision:
1. Create and use dc setup file.
2. Start with the same rtl code that is used for simulation and synthesize it.
3. The optimized netlist is created.
Q. How to simulate this netlist in vcs?




Thanks
 

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