FPGA VHDL code for VSP2560PTR (CCD)

Hi,

I'm new to VHDL FPGA programming and trying to code TI VSP2560PTR (https://focus.ti.com/lit/ds/symlink/vsp2560.pdf). Can anyone please provide me sample code, which might help me to program this or ADC or CCD sensor (ELIS1024)? I'm using Xilinx Spartan 3an development kit.

Thanks,

Hi,

Just recently completed prototype testing on design using TLV990-21 ccd processor (similar to VSP2560) and ILX554B linear ccd (2048 pixels). Have some VHDL written for Xilinx Spartan 3. Maybe you could adapt some of it.

Cheers

scanman,

That will be great. Where I can find it?
Thanks

Techie8,

It looks like the ELIS1024 is a CMOS device with 2.7V output. Nice simple chip to use compared to regular CCD which has 1V output. The 2560 chip is designed mostly for CCD as it only can handle 1.3V input range. Normal CCD operation requires correlated double sampling (sample reset reference level and then sample video level take difference), input clamping, dummy / black pixel calibration, programmable video gain etc. If you are using ELIS1024 then you could probably use an OP Amp to scale the output to 0 - 10V and correct the offset (see spec sheet). Then you could use fast AD and input data to FPGA. Calibration would have to be done differently than CCD as ELIS1024 doesn't seem to have optical black pixels. Sorry if you think I am complicating things, but I try to simplify it for you so you can have success faster.
What is your electronics experience ?
Have you coded any HDL at all ?

Scanman

Scanman,

Thanks for these details. I have gone through the datasheets for both but I'm kind of new with the FPGA programming. Could you explain a bit to me about how I could set SHP/SHD signal for VSP2560 and link it to the CCD input? Timing diagram for it is given on page 7 of the VSP2560 datasheet

OK Techie8,

I am giving you some HDL and a testbench to run it. I have changed the signal names to reflect VSP2560. This is for you to learn with. Please note this will work with ILX554B CCD. CMOS sensors like ELIS1024 will require much different and simpler design. I believe that output of CMOS pixel data is single level and not two levels (reset and video) like CCD. If you use Correlated Double Sampling on CMOS you would get difference of two samples of same voltage = zero. Please correct me if I'm wrong (still learning too). Let me know how it goes.

Cheers,
Scanman

Hi Scanman,

Typically CMOS Image sensors do CDS ( correlated double sampling ) on-chip. So a opposed to CCD there is no need to do CDS off-chip.

In CMOS sensors CDS is done to reduce the pixel KTC noise of the pixel and reduce FPN of the pixel.

Depending on the CMOS Image sensor one still need to do off-chip channel FPN correction i.e. substract an black reference image from the grabbed image.


E-goe

Hi E-goe,

Thanks for notes.
So, do you think the ELIS1024 requires anything more than dark correction?
Found this app note:

**broken link removed**

scanman

Hi Scanman,

Dark correction is an offset correction method. Another sensor/pixel non-ideality one can calibrate for is PRNU ( Pixel response Non Uniformity ) caused by gain variation between the pixels.

In order to correct for PRNU/ gain mismatches one can do the following:
1. Allow system temperature to stabilize
2. Capture a 'grey' scale image i.e uniformally illuminate the sensor so the average value is around half scale ( i.e between saturation level and dark level )
3 Perform gain correction

In order to be sure drift ( due to temp, voltage variation .... ) doesn't influence your off-line calibration's it's probably needed to re-calibrate your sensor from time to time.

Ps. Can you check the PRNU of the sensor? Maybe it's already good enough and no off-line PRNU correction is needed.


E-goe

Hi scanman !
I want to make an linear ccd scanner with FPGA to start with FPGA domain....
I have nbackground of microcontroller but not with FPGA.
Can u guide me how to drive ILX553 clock input pins?
Because in the datasheet not much help is given...

thanks n regards.