# JK Flip flop asynchronous counter

1. ## JK Flip flop asynchronous counter

Does anybody know how to build an asynchronous counter that counts from 2 to 9 with JK Flip Flops?

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2. ## Re: JK Flip flop asynchronous counter

Hi quietfoot,

You have to use 4 JK flip-flops, with asynchronous set and clear. Wire the JK FFs as T FFs by connecting J & K pins to a logic high. Connect the Q output of first FF to the CLOCK input of next FF and so on.

Next you need a combinational logic which upon detecting a '1010' (decimal 10) on output clears FFs 1,3,and 4 (through the asynchronous clear pins) and presets FF 2 (through the asynchronous set pin).

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3. ## Re: JK Flip flop asynchronous counter

@matbob

Solution looks perfect, but we need to detect 1001 (Decimal 9) and set/clear the flops asynchronously.[/quote]

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4. ## Re: JK Flip flop asynchronous counter

Dear freind
for this purpose you have to make a table of what number it shows now and what number it should show with the next lock.since you want your counter to count 2 to 9 you can either 1-use 3 flip flip and design a decoder which convert number 0 to 7 to 2 to 9 or 2-use 4 flip flops.which I recommend the second choice.
this way you can write like this:
now / next clock
0010 / 0011
0011 / 0100
... / ...
to: 1001 / 0010
after making this table you compare the similer bits in each row. and using the j_k flip flop trigger table you can decide how to use gates in input of these flip flops.
as you see it is so easy.just it takes some time!
Good luck!

5. ## Re: JK Flip flop asynchronous counter

quietfoot,
The approaches suggested by matbob and sheikhalipour will work. However, using the asynchronous set and clear inputs suggested by matbob has a potential problem: Suppose in going from states 0111 to 1000, th 2nd LSB bit (2^1) is slightly slower in switching than bits 2^0, 2^2 and 2^3. In this case, the counter would momentarily go to the state 1010, possibly causing a reset to state 0010. I t would be safer to decode state 1001, and use flip flops with synchronous set and clear inputs. This way any momentary false states would be ignored, since they would go away before the next clock pulse. This is the classic "Race" problem.
Regards,
Kral

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