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An information about timing constraints in Design Compiler

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always84

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I've a design full custom I wanto to synthetize and optmize my design. A part design rules, I can put optimization constraint. How can estimate input delay. I start in a top down synsthesis optimization flow after synthesis how can I estimate optimization constraint like input/ouput delay on timing paths? When do I have to put them ? I've read synopsys manual the explain wath this parameters are but don't explain how to estimate them.
 

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