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What is the purpose of "Verilog-XL" tool in Cadenc

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what the purpose of "Verilog-XL" tool from Cadence? the options available in Verilog-XL's are:

1. Incisive verification environment
2. Incisive P2C Methodology
3. Incisive Design Team simulator
4. Affirma simulation analysis environment

is it the option only for .sv file and its compiling, elaborating and simulation or
can we do the .vhd and .v file's too ?

plz help.
 

Re: What is the purpose of "Verilog-XL" tool in Ca

in the past, only use "Verilog-XL" to do verilog code simulation!
 

Re: What is the purpose of "Verilog-XL" tool in Ca

kk.thankx for reply

can you mention the purpose of the following options in Verilog-XL

1. Incisive verification environment
2. Incisive P2C Methodology
3. Incisive Design Team simulator
4. Affirma simulation analysis environment

thankx in advance
 

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