Queires need urgent solution for it ,please do help me out

gmailbond said:

Please do provide some solutions for these queries as i need to know the solutions

Somebody correct me if I am wrong...

1. What kind of issues or a report does a Backend Physical Design guy give to the Synthesis guy ones he has received the netlist.
And what checklist should be done by th PD guy before starting off the flow.
* If the floorplan size is fixed, the PD guy should look for the utilization after loading the netlist. If utilization more than the expected value, it means lot of cell have been added in the netlist during synthesis.
* Can check for multi-driven nets, undriven nets and dangling nets.

2.How do you solve CTS issues other than adding buffers and is there any other types of techniques other than H-tree and X-tree.
* Clock gate decloning and cloning.

3.Why do we use different VDD and VSS straps for Analog and Digital blocks (other than noise immunity issue).
* At times they operate at different voltage levels.

4.While doing the IR drop analysis i we find any IR drop we usually add more nos of straps.So what other technique can be used to solve it.
* By changing the placement if the issue is spotted at an earlier stage.

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