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Problem with simulation results of a design with asynchronous FIFO

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jacobiLL

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Hi ,all.
I have a asynchronous FIFO in my design, I found the simulation results is different between RTL and netlist. It is caused by the asynchronous FIFO, at the mistake time, the read clock and the write clock is very close(0.5ns), the netlist output is late than the RTL output.
I wonder to know is it unavoidable for the asynchronous FIFO? Use Gray code can only reduce probability of this unexpected error.
 

Re: asynchronous FIFO

jacobiLL,

I sounds like either you're using the fifo incorrectly, or the fifo was incorrectly designed.

The reason a gray count is used when crossing clock domains is that only a single bit is changing at a time. This means that you will never get a wrong value when sampling, at worst case you will get a delayed value.

I believe most async fifos uses gray counts and most of them work just fine if the rest of the logic is implemented correctly.

Radix
 

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    jacobiLL

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asynchronous FIFO

Thank you ,radix.
You're right ! The asynchronous FIFO in my design has a rd_count which indicate the number left in fifo. At the worst case the rd_count is delayed one read clock period than normal. I think this is unavoidable.
 

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