casey480
Junior Member level 1
I am attempting to design a clock tree for a design with clock gating. I am having trouble understanding the syntax for the ctcsh.
My design gates a clocks for power and functionality. In each case, devices clocked by the gated clock are expected to be synchronous with devices clocked by the ungated clock.
Should I time through the enable/clock in the latch of the clock gate? Should i turn NoGating to Rising? (i use neg level transparent latches for my gates) or leave it at NO? Should I be worried about timing to the D enable of the latch?
What about gating clocks with the negative edge of a flip flop rather than a latch? Do they need the same treatment?
My design gates a clocks for power and functionality. In each case, devices clocked by the gated clock are expected to be synchronous with devices clocked by the ungated clock.
Should I time through the enable/clock in the latch of the clock gate? Should i turn NoGating to Rising? (i use neg level transparent latches for my gates) or leave it at NO? Should I be worried about timing to the D enable of the latch?
What about gating clocks with the negative edge of a flip flop rather than a latch? Do they need the same treatment?