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Time delay in SV Assertions

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vivek4m

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Hi Friends,

I need to use a time delay (not clock cycles delay) in one of my systemverilog assertions. It will be a great help if anyone could give me an insight of whether I can do it or not? If yes, then how can I do it.

I am looking for a way to implement something like this:

property delay_problem;
@(posedge clk) disable iff(reset)
seq_a |-> #50 seq_b;
endproperty

For this I get an error:
Error-[SE] Syntax error: token is '#'

Please help.

Thanks & Regards
Vivek
 

vivek4m said:
Hi Friends,

I need to use a time delay (not clock cycles delay) in one of my systemverilog assertions. It will be a great help if anyone could give me an insight of whether I can do it or not? If yes, then how can I do it.

I am looking for a way to implement something like this:

property delay_problem;
@(posedge clk) disable iff(reset)
seq_a |-> #50 seq_b;
endproperty

For this I get an error:
Error-[SE] Syntax error: token is '#'

Please help.

Thanks & Regards
Vivek
Click to expand...

Vivek,
SVA uses cycle based semantics - meaning it requires a clock (or more). You can however achieve this by calling a sequence_match_item that can be a task call on the consequent.

Pseudo-code below:

Code: 
property delay_problem;
  @(posedge clk) disable iff(reset)
  seq_a |-> 1,b1, check_after_50();
endproperty

  task check_after_50();
    #50ns; if (seq_b == 1) ..;

HTH
TeamCVC
www.cvcblr.com/blog
 

Thanks a lot. I think it will help me :D .
 

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