Problem with testbench in 16-bit CLA code in VHDL

Hello! i'm new to digital design, especially VHDL. I've designed a 16-bit CLA code and a testbench for it but i'm having difficulty with the testbench part.
It won't even compile and i can't find where i've gone wrong. It would be a great big help if you could lend me a hand. So, here's the code(testbench)

library ieee;
use ieee.std_logic_1164.all;

entity CLA_16bit is
end CLA_16bit;

architecture tb of tb_CLA is
component CLA_16bit is
port ( a_in : in std_logic_vector (15 downto 0);
b_in : in std_logic_vector (15 downto 0);
c_in : in std_logic;
s_out : out std_logic_vector (15 downto 0);
c_out : out std_logic;
overflow : out std_logic);
end component;

signal a_in, b_in : std_logic_vector (15 downto 0);
signal c_in : std_logic;
signal s_out : std_logic_vector (15 downto 0);
signal c_out, overflow : std_logic;

begin
tb_CLA : CLA_16bit port map(a_in, b_in, c_in, s_out, c_out, overflow);
process
begin
wait for 10ns;
a_in <= '1000000000001001';
b_in <= '1000000000001001';
c_in <= '0';
wait for 10ns;
a_in <= '1010101010101010';
b_in <= '0101010101010111';
c_in <= '1';
wait for 10ns;
a_in <= '0101010101010101';
b_in <= '0101010101010101';
c_in <= '1';
wait for 10ns;
a_in <= '1111111111111111';
b_in <= '0000000000000001';
c_in <= '0';
wait for 50ns;
end process;
end tb;

Re: 16-bit CLA VHDL

1-
ENTITY toto IS
END ENTITY toto;

ARCHITECTURE tb OF toto IS
END ARCHITECTURE tb;

2- "wait for 10ns", need space between value an unit

3- for vector with more than one bit, using "00" instead '0', '00' not allowed

to have more clear code, a 16bits can be written like this a_in <= x"1234"; means one digit is 4bits.

Take care if you have the signal declare as 17bits, you can wrote
t <= x"12345";
but
t <= '0'&x"1234"; (concatenate single bit with 4*4bits => 17bits)