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poles & zeros location in a given circuit

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jimito13

jimito13

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Hello,

I have a very general and theoritical question.Suppose we are given an analog CMOS circuit,how can we know in advance (before making hand calculations) where (at which node) the poles and zeros of the circuit are located?I would appreciate any helpful answer or some references to read.
 

You can read some LDO paper form IEEE and you will benefit from it to analyse the pole zero of the circuirt.
 

Can you be more precise please?What is LDO paper??Thanks.
 

Hi,

u r 1st question is quite interesting one.. one option will b symbolic circuit analsys.. there are few tools/algorithms available for it.. nvr happen 2 try it myself...

the othr alternate is... draw the ac small signal model of the ckt ... this should include the parasitic devices (Rs & Cs).. thn do approximate the time constant for each node..you can get approx. P/Z locations.. and dominant ones..

But this is tedious if the ckt is big.. always u can use pzanlysis in SPICE

Hope this helps...
 

blackuni thanks for your answer.I am aware of these methods you proposed me.But my question is more theoritical and intuitional and concerns an approach to my problem that does not require from somebody to make hand calculations or circuit analysis.Maybe i was not much clear to my first post...i don't care about the exact equation that gives me the poles and zeros of an analog cmos topology but i care about their position,that is at which node we expect to have a pole or zero or pole zero doublet.ofcourse i do not know if this approach is feasible,but in any case that's why i opened this question.thanks for any future helpful feedback.
 

Every single node will have an associated pole... now the question is... how to know which are the MOST relevant poles and zeros in a circuit? The only way of know this, without not a single equation is... experience.
 

Thanks diemilio.How can we explain or prove mathematically that a high impedance node is related with low frequency poles and a low impedance node causes high frequency poles?If there is any relevant reference (book or paper) i would appreciate a proposition.Thanks in advance.
 

jimeece13 said:
If there is any relevant reference (book or paper) i would appreciate a proposition.
Click to expand...

You can find explanation of this concept in Razavi "Design of Analog CMOS Integrated Circuits", section 6.1.2 "Association of Poles with Nodes" (p. 169).
 
Sorry... I don't know any papers in particular that discuss this subject. I think textbooks are probably a better source for this kind of things.

diemilio
 

thanks dedalus,i just gone through chapter 6 of razavi and it was helpful to my question indeed.

Regards
 

the node which has large resistors and capacitors will generate poles.take a miller opamp as an example, hope you can benefit from it
 

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