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Layout problems in capacitor array

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liushaotao

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I am working on 12-bit SAR ADC design, in which i make use of capacitor array to build DAC block. All simulations work fine in schematic simulations. However, when I did a post layout simulation on DAC block, the result is very bad. In the DAC block, I need a few switches to control the capacitor DAC. When I connect the switch to capacitor array in the layout, the result is very bad; however, when I test
the capacitor alone, it works well. Can any one tell me the problem? The capacitor I use is cploy 1pF; the switch I use is nMos, 0.4x0.35 (minimum size); I use AMS 0.35 process.
 

It would be useful to know what "very bad means". Is it inaccurate or glitchy for example? Did you initial simulations use a capacitor model which included the capacitance to substrate?

Keith.
 

What kind of topology are you using?? Do you have any "series" capacitors in the circuit? or are all of them referenced to ground?

diemilio
 

maybe you need to separate the digital signal from the cap. and many shielding needed in the array.
 

diemilio said:
What kind of topology are you using?? Do you have any "series" capacitors in the circuit? or are all of them referenced to ground?

diemilio
Click to expand...
I am using cpoly. capacitors and switches are all referenced to gnd.

Added after 4 minutes:

keith1200rs said:
It would be useful to know what "very bad means". Is it inaccurate or glitchy for example? Did you initial simulations use a capacitor model which included the capacitance to substrate?

Keith.
Click to expand...
Large inaccuracy problem. It is supposed to switch from 1V to 1.5V, but accutually it can only reach 1.42 V. All the capacitors and switches I use are built on P substrate. I also implemented guard rings on the capacitor array, but the results is still inaccurate.
 

I think I would need to see the circuit & preferably some simulation results. The capacitance is quite high and the switching transistor quite small so I wonder if the transistor is too small, depending on the switching speed?

Keith.
 

Problems solved! It is bcoz i use ploy1 as common plate to connect to the output. The paracitic capacitance between ploy1 and substrate is very large. For AMS 0.35, the ratio of poly1 capacitor and paracitor capacitor is about 7/1. So the total paracitic compacitance added to the output port is over 3pf for my design, which caused a very in acuuracy problems. Thank all
 

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