Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi Aurorel,
IC Compiler is supporting SV designs, you'll get any supoports from Synopsys on that.
But the reply from ljxpx is misleading, "irun" command will work for the Cadence Simulation tools, not for the Synopsys Compiler tools!!!
Thanks, paulki. I was trying to run an SV design, and ICC was complaining on the always_comb and other SV constructs. So, how do I go about fixing this with Synopsys?! Thanks.
Check in the Synopsys Solvenet site any additional switches (+sv) are required to pass while doing ICC for the SV designs. This will help you to resolve the issue.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
