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About the center tap inductor of IBM 90nm process

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shahriar22nd

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Hi all,
I was designing a circuit, having an inductor, in cadence virtuoso with ibm 90nm pdk. Inductors of this pdk have optional center taps. However, I do not need the center tap. So, I unchecked the 'include centertap wire?' option in the create instance box both in schematics and in layout. It worked for the pcells of the layout- no center tap appeared, but did not work for the schematic symbols. The center tap is always present in the schematic symbol and is creating floating pin warning when check and saved.
Could anyone please write me, how the center taps of the inductors of ibm 90nm technology can be eliminated, specially from the schematics ?
Thank you.
 

shahriar22nd said:
... how the center taps of the inductors of ibm 90nm technology can be eliminated, specially from the schematics ?
Click to expand...
You can't remove it - they probably use the same symbol for both. If you don't use the center tap, just put the noConn symbol from the basic lib on it - like on any other unused pin.
 

Thank you erikl for your reply. It was a new idea for me. Anyway, I was thinking about the LVS. In this case, the center tap is present in the schematic but is not connected, whereas, the tap is either present or not in the layout pcells depending on my selection from the 'add instance' box. So, what is to do with the "include centertap wire?" field from the add instance boxes to pass LVS? shall I de-select it both for the schematic and from the layout ?
Thank you.
 

shahriar22nd said:
... what is to do with the "include centertap wire?" field from the add instance boxes to pass LVS? shall I de-select it both for the schematic and from the layout ?
Click to expand...
Actually I don't know, but I'd suppose so. Just give it a try!
 
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