Transistor o/p signal voltage swing

Hi aLL
For the following Fixed bias emitter stablized circuit
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the voltage swing from Vcc to Isat RE; that is the ac signal is carried on VC dc voltage and swing up from Vc to Vcc and down from Vc to Isat RE.
My question about the second fixed bias circuit that follows
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is the voltage swing from VCC up to zero down?
Is it from VCC up to Isat re down, where re is 0.026/IE?
please help.
Another question: For the second circuit If Rc= 1.5K and RB=540k
what the maximum peak-to-peak i/p signal voltage that can be amplified without distortion.
thank you alot.

Yes the voltage swing will be from VCC up to zero down, ideally. There is always some voltage drop in the resistor and the transistor, (about 100mV).

About the second question could only be answered if we knew the β (or Hfe) of your transistor and supply voltage. When amplifying a signal there will ALWAYS be some distortion because no transistor is absolutely linear. However this distortion only becomes critical when your output signals amplitude comes close to VCC or GND.

So if you want to avoid distrotion keep your output signal at a 300 mV distance (minimum) from both Saturation and Cut Off.

fcfusion said:

Yes the voltage swing will be from VCC up to zero down, ideally. There is always some voltage drop in the resistor and the transistor, (about 100mV).

Click to expand...

Are u mean the first circuit?

About the second question could only be answered if we knew the β (or Hfe) of your transistor and supply voltage. When amplifying a signal there will ALWAYS be some distortion because no transistor is absolutely linear. However this distortion only becomes critical when your output signals amplitude comes close to VCC or GND.

So if you want to avoid distrotion keep your output signal at a 300 mV distance (minimum) from both Saturation and Cut Off.

Click to expand...

I design the second circuit as: Vcc = 3 V, IC= 1mA, 2N3904 transistor β=230
VBE=0.67 volt from the datasheet
thanx

Hello,

Both circuit have strong dependence on HFE (that varies per device [see data sheet]) and with temperature), so your Vce will not be half the supply (or somewhat above for the upper circuit).

The lower circuit will have significant distortion, especially when driven from a voltage source. When you have significant swing (but not saturating), you will even notice that on the oscilloscope graph.

The first circuit may have significantly less distortion when RE >> 1/(40*Ic).

re (1/(40*Ic)), is not a real resistor that is in the collector, but relates to the transconductance of the transistor (ic/vbe small signal). The saturation voltage can be very low (100mV or even less).

Look in to the datasheet of many transistors. Especially at low collector current (were bulk resistance doesn't introduce additional voltage drop), Vcesat can be very low. The modern multi cell low Vce-sat transistors (NXP, Zetex/Diode) can have saturation voltages in the 10mV range.