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scaling gate sizes in Cadence Spectre for logical effort

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pvvikas

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In Hspice, a sub circuit can be defined for an inverter and a scale parameter could be defined like this

.subckt inv in out k=1
xmp out in vdd vdd pfet w='2*k*140n' l=90n
xmn out in gnd gnd nfet w='k*120n' l=90n
.ends


Later, this inverter can be called by using

x1 vin vout inv k=4

here k=4 scales the inverter sizes by 4 times.

I was just wondering if one could do this in Cadence Spectre since it is a really robust and industry standard tool. The sizes for an inverter in Cadence could be defined as 'k*120n' but we cannot call instances of it with different values of 'k' in the higher level schematic.

Please help.

thanks,
Vikas
UT Dallas
 

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