buenos
Advanced Member level 3
- Joined
- Oct 24, 2005
- Messages
- 960
- Helped
- 40
- Reputation
- 82
- Reaction score
- 24
- Trophy points
- 1,298
- Location
- Florida, USA
- Activity points
- 9,116
Hi
Is there a standard VHDL or verilog solution (a wrapper or something) for implementing a back-end interface for the PCI-express endpoint block in Xilinx (spartan-6) FPGAs?
The coregenerator generates 450 signals as user interface, and its not exactly a bus. It needs a bus state machine, for example OPB or Wishbone.
Is there a standard VHDL or verilog solution (a wrapper or something) for implementing a back-end interface for the PCI-express endpoint block in Xilinx (spartan-6) FPGAs?
The coregenerator generates 450 signals as user interface, and its not exactly a bus. It needs a bus state machine, for example OPB or Wishbone.